This invention relates to a semiconductor memory device such as a DRAM and method of manufacturing same.
In the conventional semiconductor memory device such as a one-transistor/one-capacitor type DRAM, the technique for increasing the storage node height in the height direction of the memory cell is apt to be employed to increase the cell capacitance as in the stacked DRAM memory cell structure (hereinafter, referred to as "STC structure") because the increase of the surface area of the capacitor portion is limited in terms of the memory size. The dependency on this technique becomes greater as the integration density of the DRAM increases. Some examples of the STC structure are described in, for example, NIKKEI MICRODEVICES, July 1994 (published by NIKKEI Business Publications, Inc.), pp 32-37.
However, increasing the height of the memory cell portion of the STC structure makes the level difference larger between the cell array section and the peripheral circuit section. Thus, when patterning the metal conductors, such as bit lines, formed over the cell array and peripheral circuit sections, it will be difficult to achieve a high resolution for fine-pattern conductors because of lack of the DOF (Depth Of Focus) margin of photolithography. In other words, since the pitch of the bit lines becomes narrow with the decrease of the distance between the cells, the above problem becomes serious. The DOF margin in this photolithography is not described yet in the NIKKEI MICRODEVICES given above.